Providing Fast And Safe Access To Next-Generation, Non-Volatile Memories

Joel Coburn, Google

Stevenson Hall 1300
11:00 AM - 11:50 AM

Emerging non-volatile memory technologies such as phase change memory, spin-torque transfer memory, and the memristor, will provide many orders of magnitude decrease in latency compared to disk and flash memory, dramatic increases in bandwidth, and a byte-addressable interface similar to DRAM. These new memories offer the possibility of enormous performance gains, but fully realizing them will require us to rid software of disk-centric optimizations, design decisions, and architectures that limit performance and ignore bottlenecks that the poor performance of disks have hidden in the past. The algorithms and architectures that storage and database systems use to enforce strong consistency guarantees are especially important to system performance, and current solutions are deeply tied to conventional disk technology. This work addresses the problem of providing transactional support for fast, non-volatile memories that can make programming easy and exploit the raw performance of these new technologies. First, we present a prototype PCIe-based storage array that targets fast, non-volatile memories and provides hardware support for multi-part atomic write operations. Unlike previous approaches for flash-based SSDs, our atomic write support makes logging scalable and transparent to the user, providing a strong foundation for implementing full transactions. Using multi-part atomic writes we show how existing transactions mechanisms such as ARIES can be redesigned to make optimal use of these memories. Second, we consider how to provide safety for storage that is directly accessible via the processor's memory bus. We present NV-heaps, a persistent object store which provides a familiar programming interface and protects against application and system failures by avoiding familiar programmer errors as well as new errors that only arise with persistent objects.