Managing Memory Smartly

Jason Lowe-Power
Assistant Professor University of California, Davis

Stevenson Hall 1300
12:00 PM - 12:50 PM

Managing the data movement is a major bottleneck in many computing systems. Today, there is an explosion in data set sizes. For instance, terabytes of active memory are required for training machine learning models. Unfortunately, at the same time there has been relatively little growth in the capacities of memory devices. These trends are leading to increasingly heterogeneous memory systems with a small amount of high-performance memory and high-capacity memories with lower performance. In this talk, I will explain why hardware-managed data movement techniques perform poorly in these heterogeneous systems, and I will describe a software-based technique, AutoTM, which outperforms a hardware DRAM cache. Further, I will discuss our ongoing work developing a "data management ISA" to enable software-directed and hardware-accelerated heterogeneous memory management.

Bio: Jason Lowe-Power is an Assistant Professor at University of California, Davis where he leads the Davis Computer Architecture Research Lab (DArchR). His research interests include optimizing data movement in heterogeneous systems, hardware support for security, and simulation infrastructure. Professor Lowe-Power is also the Chair of the Project Management Committee for the gem5 open-source simulation infrastructure. He received his PhD in 2017 from the University of Wisconsin, Madison, and received an NSF CAREER Award and a Google Research Scholar Award.